Resilience-Driven STT-RAM Cache Architecture for Approximate Computing

High-end manycore microprocessors exhibit large-sized caches (32MB – 128MB) that consume a significant amount of total energy. These caches are typically composed of 6T-SRAM cells, which lack efficiency in terms of area and leakage power [1][2]. The emerging memory technologies, like Spin-Transfer Torque RAM (STT-RAM), not only incur reduced leakage power but also provide high integration density and resilience to soft errors [3]. Due to their high write latency/power, such non-volatile memories are mainly deployed at lastlevel caches [1]. The Multi-Level Cells (MLC) STT-RAM technology allows storing more than one logic bit in a physical memory cell by further discretization of the resistance range of the magnetic tunnel junction. The resulting capacity improvements facilitate large-sized memory banks, as shown by the recent studies in [4][5]. However, process variations result in tight sense margins between adjacent resistance states that lead to frequent errors during the read/write operations [4]. As a result, the MLC STT-RAM requires error correction circuitry to ensure reliable memory operations. This incurs a non-negligible protection overhead compared to the Single-Level Cells (SLC) STT-RAM. Therefore, a key research challenge is to enable energy-efficient reliability for MLC STT-RAM cache memories.